a. Field of the Invention
The present invention pertains to integrated circuit development and more specifically to employing standard cell tools in the simulation and verification of custom circuit designs.
b. Description of the Background
Integrated circuit designs may employ custom, semi-custom, or a combination of custom and semi-custom design methodologies. Custom refers to the creation of a new physical layout for each design. Semi-custom refers to the use of predefined circuit elements. Semi-custom methodologies include gate array and standard cell. Gate arrays employ a set of predefined functions fabricated on a semiconductor wafer that may be later interconnected to implement a design. Standard cell technologies provide a library of low-level circuit functions each having a predefined physical layout. The predefined physical layout, or cells, typically have a common dimension such as width or height such that they may be placed in rows and blocks, the order determined by functions to be implemented and routing of interconnect between cells or groups of cells.
In developing an integrated circuit, a designer may partition a design into various functional blocks and then design circuitry for each functional block or re-use a design for a functional block if a previous design meets size, power, and performance criteria. Circuit design most frequently employs a hardware descriptive language (HDL) that specifies circuit elements and the connection between elements. Verilog® is a commonly used HDL and is the topic of IEEE Std 1364. Verilog is a registered trademark of Cadence Design Systems, headquartered in San Jose, Calif. Verilog may be used to specify the initial design, to provide input to simulation and synthesis tools, and to check post layout operation.
At times, the predefined set of cells of a standard cell library may not provide a desired function, or may not provide the speed, size, or power consumption desired. In these circumstances, new cells may be created, or a custom block of logic incorporating the desired function and capabilities may be designed. The design of the custom block of logic may employ SPICE (Special Programs for Interactive Circuit Elements) to specify and simulate the design. Some product versions of SPICE support both logical and timing simulation. However, SPICE simulation is extremely slow when compared to simulation employing an HDL netlist, such as a Verilog, as is commonly employed for standard cell designs. When designs comprise standard cell and custom logic sections, a problem arises when attempting to simulate the entire design. The custom logic may exist simply as a “black box” wherein operation of standard cell and custom logic are separately simulated but simulation comprising both sections is not performed. A behavioral model, such as may be written in a programming language such as “C”, for example, may be employed for functional simulation, but such models do not allow timing analysis. Due to the limitations of present methods, a new method is needed that allows simulation of both standard cell and analog circuits with timing analysis without requiring extensive simulation time or computing resources.